The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming strained <100> n-channel field effect transistor (NFET) fins and adjacent strained <110> p-channel field effect transistor (PFET) fins on the same substrate.
In each new generation of semiconductor technology, transistor current decreases due to gate width reduction, mobility degradation of minority carriers, and reduction of supply voltage. Reduced transistor current results in deterioration of circuit stability and reduces the speed of circuit operation thereby causing degradation in performance.
In some field effect transistor (FET) devices, the introduction of strain (e.g., compressive or tensile) to a channel region of a FET may be used to improve carrier mobility, which may subsequently increase FET performance. Tensile strain may be used to improve electron mobility, and compressive strain may be used to improve hole mobility. In addition, forming a channel region of a FET with a particular crystallographic orientation may result in increased performance. Specifically, electron mobility may be higher in a <100> crystallographic orientation, while hole mobility may be higher in a <110> crystallographic orientation. However, forming a substrate comprising one or more channel regions with individually tailored strain and crystallographic orientation is challenging.